Bipolar transistor

ABSTRACT

A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages.

FIELD OF THE INVENTION

The present invention generally relates to semiconductor devices andcircuits and methods for fabricating semiconductor devices and circuits,and more particularly relates to semiconductor devices and circuitsembodying bipolar transistors.

BACKGROUND OF THE INVENTION

Bipolar transistors are much used in modern electronics as individualdevices and as part of various integrated circuits (ICs). It is oftendifficult to simultaneously achieve certain combinations of desiredproperties, as for example and not intended to be limiting, both highgain and high Early Voltage with adequate breakdown voltages. In theprior art it has been customary to tune the properties of particulardevices by, for example, adjusting the doping profiles. However, inlarge scale production this may not be practical since manufacturingoptimization and cost considerations often limit the variations indoping profiles that can be used in the manufacturing sequence for aparticular semiconductor device or IC. Accordingly, a need continues toexist for improved bipolar transistors and methods for manufacturing thesame, which permit both high gain and high Early Voltage to besimultaneously achieved using common manufacturing techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and wherein:

FIG. 1 shows a simplified cross-sectional view about a centerline of animproved bipolar transistor according to an embodiment of the presentinvention;

FIG. 2 shows a simplified cross-sectional view about a centerline of animproved bipolar transistor according to another embodiment of thepresent invention; and

FIGS. 3-9 show simplified cross-sectional views of the bipolartransistors of FIGS. 1-2 during various stages of manufacture, accordingto further embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is merely exemplary in nature and isnot intended to limit the invention or the application and uses of theinvention. Furthermore, there is no intention to be bound by anyexpressed or implied theory presented in the preceding technical field,background, or the following detailed description.

For simplicity and clarity of illustration, the drawing figuresillustrate the general manner of construction, and descriptions anddetails of well-known features and techniques may be omitted to avoidunnecessarily obscuring the invention. Additionally, elements in thedrawing figures are not necessarily drawn to scale. For example, thedimensions of some of the elements or regions in the figures may beexaggerated relative to other elements or regions to help improveunderstanding of embodiments of the invention.

The terms “first,” “second,” “third,” “fourth” and the like in thedescription and the claims, if any, may be used for distinguishingbetween similar elements or steps and not necessarily for describing aparticular sequential or chronological order. It is to be understoodthat the terms so used are interchangeable under appropriatecircumstances such that the embodiments of the invention describedherein are, for example, capable of operation or arrangement insequences other than those illustrated or otherwise described herein.Furthermore, the terms “comprise,” “include,” “have” and any variationsthereof, are intended to cover non-exclusive inclusions, such that aprocess, method, article, or apparatus that comprises a list of elementsor steps is not necessarily limited to those elements or steps, but mayinclude other elements or steps not expressly listed or inherent to suchprocess, method, article, or apparatus. The term “coupled,” as usedherein, is defined as directly or indirectly connected in an electricalor non-electrical manner. As used herein the terms “substantial” and“substantially” mean sufficient to accomplish the stated purpose in apractical manner and that minor imperfections, if any, are notsignificant for the stated purpose.

As used herein, the term “semiconductor” and the abbreviation “SC” areintended to include any semiconductor whether single crystal,poly-crystalline or amorphous and to include type IV semiconductors,non-type IV semiconductors, compound semiconductors as well as organicand inorganic semiconductors. Further, the terms “substrate” and“semiconductor substrate” and “SC substrate” are intended to includesingle crystal structures, polycrystalline structures, amorphousstructures, thin film structures, layered structures as for example andnot intended to be limiting, semiconductor-on-insulator (SOI)structures, insulator-on-semiconductor structures (IOS), andcombinations thereof.

For convenience of explanation and not intended to be limiting,semiconductor devices and methods of fabrication are described hereinfor silicon semiconductors, but persons of skill in the art willunderstand that other semiconductor materials may also be used.Additionally, various device types and/or doped SC regions may beidentified as being of N type or P type, but this is merely forconvenience of description and not intended to be limiting, and suchidentification may be replaced by the more general description of beingof a “first conductivity type” or a “second, opposite conductivity type”where the first type may be either N or P type and the second type isthen either P or N type. Various embodiments of the invention will beillustrated for NPN bipolar transistors, but this is merely forconvenience of description and is not intended to be limiting. Personsof skill in the art will understand that PNP transistors and othersemiconductor devices and circuits embodying either or both NPN and PNPcombinations may be provided by appropriate interchange of conductivitytypes in the various regions.

For convenience of description and not limitation, the custom isfollowed of identifying exemplary conductivity types of particularsemiconductor regions, and the preferred formation technique whereappropriate, by including such identification in the various figures inparentheses by way of example and not limitation. For example, for anNPN bipolar transistor, the emitter may be identified (N+), the baseregion as (P) or (P-EPI), and the collector region as (N) with an (N+)collector contact, etc. Persons of skill in the art will understand thatthis is merely by way of example and not limitation, and that otherdevice types may be prepared by appropriate interchange of conductivitytypes, fabrication techniques and doping concentrations.

Adjusting doping profiles to suit particular device needs is astraightforward way to optimize device properties. However, adding ormodifying process steps to provide a desired bipolar devicecharacteristic generally adds cost and complexity. This is especially ofconcern for processes used to manufacture multiple device types at thesame time on the same manufacturing line and/or substrate. Accordingly,a need exists for improved bipolar transistors and methods formanufacturing the same: (i) that are adapted to being “tuned” to suitparticular applications, (ii) that accommodate a wide range of designspace with little or no compromise of other properties, and (iii) thatcan be accomplished by layout adjustments without adding orsignificantly modifying process steps that would increase manufacturingcost. With the embodiments described below, bipolar device propertiescan be substantially modified just by layout adjustments. Theseembodiments can provide a wide design space without adding process cost.Thus, doping and masking steps can be shared with other devices on thewafer or chip without the bipolar transistors imposing undesirableconstraints on process optimization.

Referring now to FIGS. 1 and 2, it has been discovered that broadlytunable high gain, high Early Voltage, high breakdown voltage bipolartransistors (20, 20′) can be provided by including a multi-levelcollector structure (28) combined with a lightly doped base region (25)in which the multilevel collector structure (28) is located. Themulti-level collector structure (28) includes a relatively deepcollector tip portion (285) underlying the base contact (32), ashallower central collector portion (283) coupled to the collector tipportion (285) by a self-aligned vertically narrower intermediate portion(288) and a further main collector portion (281) coupled to the centralcollector portion (283) and extending to the collector contact region(30). The lightly doped base region (25) contributes to high currentgain. The depletable intermediate portion (288) allows the deepercollector tip portion (285) below the base contact (32) to besubstantially pinned (e.g., approximately fixed) at an intermediatevoltage so that it no longer closely follows the collector voltage athigher collector bias. This provides a high Early Voltage. Themulti-level collector structure (28) may become fully depleted at stillhigher collector voltages, thereby preserving high breakdown voltagesBVcbo and BVceo. BVcbo refers to the collector-base breakdown voltagewith the emitter open and BVceo refers to the collector-emitterbreakdown voltage with the base open. Such combination of properties isachieved using commonly available doping profiles consistent withmanufacturing a wide variety of useful devices, by taking advantage ofdopant channeling to form the multi-level collector region, and ifdesired, substantially in a single collector doping step. This is ahighly desirable combination of properties.

FIG. 1 shows a simplified cross-sectional view about centerline 19 ofimproved bipolar transistor 20 according to an embodiment of the presentinvention. Referring now to FIG. 1, transistor 20 comprise substratelayer 21 having lower or bottom surface 22 and upper surface 23.Substrate layer 21 may be a semiconductor (SC) or dielectric substrate.In a preferred embodiment for NPN transistors, substrate layer 21 is anN type SC but may be of other conductivity type in other embodiments foreither NPN or PNP transistors or may be an insulating substrate. In apreferred embodiment buried oxide (BOX) layer 24 overlies upper surface23 of substrate layer 21. Above BOX layer 24 (when present) issemiconductor (SC) base region 25, preferably an epitaxial (EPI) layerextending to upper surface 26. For convenience of description and notintended to be limiting, region 25 may also be referred to as “EPI layer25” or “EPI 25”, but persons of skill in the art will understand that SCbase region 25 formed by any means may also be used and the designation“EPI” as used herein for region 25 is intended to include other means offormation. Reference number 27 in FIGS. 1-9 is intended to refer to thecombination of substrate layer 21 and base region 25, with or withoutBOX layer 24. For convenience of description the terms “substrate 27”and “substrate (27)” are used when referring to this combination.

Referring again to FIG. 1, lying within (e.g., P:-EPI) base region 25 atupper surface 26 are shallow trench isolation (STI) regions 55-1, 55-2,55-3 (collectively 55) of thickness 56 and deep trench isolation (DTI)region 60. DTI region 60 is conventional and extends substantially fromBOX layer 24 (when present) to upper surface 26, desirably but notessentially intersecting STI region 55-1. In a conventional form, DTIregion 60 comprises polycrystalline semiconductor core 61 laterallysurrounded by dielectric layer (e.g., silicon oxide) 62, but otherlaterally isolating structures may also be used. Reference number 261identifies the location of collector contact region 30 between STIregions 55-1 and 55-2. Reference number 262 identifies the location ofbase contact region 32 between STI regions 55-2 and 55-3. Referencenumber 263 identifies the location of emitter region 34 to the left ofSTI region 55-3.

Also lying within base region 25 is (e.g., N type) multilevel collectorstructure 28. For convenience, brackets 281, 283, 284 and 288 are usedto identify the various parts of multilevel collector structure 28, asfollows: (a) “main” or “first” collector portion 281, (b) “central” or“second” collector portion 283, (c) “tip” or “third” collector portion285, and (d) “intermediate” or “fourth” collector portion 288, where thealternative labels are intended interchangeably. Deeper collectorportion 282 extends below main or first collector portion 281. Main orfirst collector portion 281 of (e.g., N type) collector structure 28extends to upper surface 26, and is coupled to (e.g., N+) collectorcontact region 30 in location 261 between STI regions 55-1 and 55-2.Main or first collector portion 281 has depth 291 from upper surface 26.Deeper collector portion 282 of (e.g., N type) collector structure 28lies below main or first collector portion 281 and extends to furtherdepth 292 in (e.g., P-EPI) base region 25 below main or first collectorportion 281. Deeper collector portion 282 is an artifact of a preferredprocess used to provide multi-level collector structure 28 and may beomitted in other embodiments.

Central or second collector portion 283 (e.g., N type) of verticalthickness 293 and depth 294 below upper surface 26 is coupled, forexample, to the left side, of main or first collector portion 281. Baseregion portion 251 of (e.g., P-EPI) base region 25 lies between centralor second collector portion 283 and STI region 55-2. Collector tip orthird portion 285 (e.g., N type) of vertical thickness 295 lies to theleft of and slightly spaced from (e.g., N type) central or secondcollector portion 283. Collector tip or third portion 285 lies at depth296 below substrate upper surface 26, its lower surface lies at depth297 below substrate upper surface 26. Depth 296 is preferably greaterthan or equal to depth 294 but other depths may also be used in otherembodiments. Base region portion 252 (e.g., P type) lies betweencollector tip or third portion 285 of collector structure 28 andsubstrate upper surface 26, and has therein (e.g., P+) base contact 32lying laterally between STI regions 55-2 and 55-3. Leftward edge 287 ofcollector tip or third portion 285 is laterally spaced distance 302 fromleftward edge 253 of base region portion 252 underlying base contactregion 32 and by about the same lateral distance 302 from leftward edge321 of base contact 32, taking into account any lateral diffusion thatmay have occurred in connection with base region portion 252. Lateraldistance 302 is desirably greater than zero but other distances may beused in other embodiments.

Connecting central or second collector portion 283 to deeper collectortip or third portion 285 is (e.g., N type) a desirably (vertically)narrower intermediate or fourth collector portion 288. Intermediate orfourth collector portion 288 has lateral width 298 and verticalthickness 299. Vertical thickness 299 of intermediate or fourthcollector region 288 is different than and desirably less than verticalthickness 295 of collector tip or third portion 285, more usefully inthe range of 1% to 90% of thickness 295 and preferably in the range ofabout 15% to 80% of vertical thickness 295. Lateral width 298 ofintermediate or fourth portion 288 is generally different than anddesirably less than the lateral width 284 of collector tip or thirdportion 285, but other arrangements can be used in other embodiments.The relatively thinner and/or narrower intermediate or fourth collectorportion 288 of multilevel collector structure 28 becomes depleted ascollector bias increases, thereby electrically separating the voltage onmain or first collector portion 281 and tip or third collector portion285. This provides high Early Voltages. Intermediate or fourth collectorportion 288 desirably has lateral width 298 substantially of at leastabout 0.01 micrometers, and vertical thickness 299 of substantiallyabout 0.01 micrometers or more, but larger and smaller widths andthicknesses can also be used in other embodiments. The potential ofcollector tip or third portion 285 is pinned after intermediate orfourth collector portion 288 is fully depleted. Once such depletiontakes place, the collector current becomes nearly independent of thecollector voltage, giving rise to a high Early Voltage. Verticalthickness 299 of intermediate or fourth collector portion 288 affectsthe collector voltage required to fully deplete the intermediatecollector portion 288, but does not significantly change the EarlyVoltage as long as full depletion has occurred. For convenience ofdescription, elements 281, 283, 285 and/or 288 of multilevel collectorstructure 28 may be referred to equivalently as regions, portions orparts 281, 283, 285 and/or 288.

Emitter region 34 lies to the left of STI region 55-3 conveniently atsubstrate upper surface 26. In this embodiment, the lateral separationof emitter region 34 and base contact region 32 is determinedsubstantially by the lateral width of STI region 55-3. Base regionportions 254 and 256 of (e.g., P-EPI) base region 25 substantiallylaterally surround collector structure 28, base region portion 255 ofbase region 25 underlies collector structure 28, and base regionportions 251, 252 of base region 25 overlie collector structure 28except where main or first collector portion 281 extends to collectorcontact region 30. As is explained more fully in connection with FIGS.3-9, the doping concentrations of base region portions 251, 252 aredesirably somewhat higher than the doping of the remainder of baseregion 25, for example by a factor in the range of about 2 to 10⁵, butdifferent doping ratios may be used in other embodiments.

Conventional semiconductor-metal alloy contact 40 with terminal 50 isprovided to collector contact region 30. Conventionalsemiconductor-metal alloy contact 42 with terminal 52 is provided tobase contact region 32. Conventional semiconductor-metal alloy contact44 with terminal 54 is provided to emitter region 34. Bipolar transistor20, described above, is able to simultaneously provide high gain, highbreakdown voltage and high Early Voltage. This is an extremely desirablecombination of properties.

FIG. 2 shows a simplified cross-sectional view about centerline 19 ofimproved bipolar transistor 20′ according to another embodiment of theinvention. Because of the close similarity of transistors 20 and 20′,the custom is adopted of using the same reference numbers to identifyanalogous regions in each device. Accordingly, the discussion of thevarious regions with like reference numbers provided in connection withtransistor 20 of FIG. 1 is incorporated herein by reference. Thoseregions that serve the same function but which may differ in some detailhave a prime (′) added to their reference numbers in FIG. 2 so that, ifdesired, they may be identified individually.

Transistor 20′ of FIG. 2 differs from transistor 20 of FIG. 1 in thatSTI region 55-3 of FIG. 1 is omitted in FIG. 2, and the lateralseparation between base contact location 262 and emitter location 263 issubstantially determined by silicide blocking (SB) region 57-3 shown inFIG. 2. As used herein, the term “silicide blocking region” is notlimited merely to materials that block the formation of silicon-metalalloys but is intended to refer to any material that can act as a masklimiting the formation of metal-SC alloy contact regions of any type toexposed SC regions (of any SC material), as for example, limitingmetal-SC alloy contact formation to emitter region 34′ and base contactregion 32′ while not forming above upper surface 26 therebetween.Silicon nitride is a non-limiting example of a suitable material forsilicide blocking (SB) region 57-3 but other dielectric material mayalso be used. As will be subsequently explained, silicide blocking (SB)region 57-3 can also conveniently act as a doping mask defining thelateral extent of emitter region 34′ and the leftward extent of basecontact region 32′, but other doping masks may be used in otherembodiments. As a practical matter, only those regions of transistor 20′to the left of multi-level collector structure 28 may differ in detailfrom comparable regions of transistor 20. The performance advantages(e.g., described above) provided by transistor 20 of FIG. 1 are alsoprovided by transistor 20′ of FIG. 2.

It will be noted that STI region 55-3 of FIG. 1 and SB region 57-3 ofFIG. 2 perform analogous functions, among other things, laterallyseparating emitter region 34, 34′ from base contact region 32, 32′, andproviding a mask used in part to define the locations of emitter region34, 34′ and base contact region 32, 32′. For convenience of description,in FIG. 1 only STI regions 55-1, 55-2, 55-3 are illustrated asseparating collector contact region 30 from DTI region 60, collectorcontact region 30 from base contact region 32, and base contact region32 from emitter region 34. In other embodiments one or more of such STIregions may be replaced by equivalent SB regions 57-1, 57-2 (not shown)and 57-3. Accordingly, the term lateral dielectric (LD) region(s) 67-iis intended to refer to either of, for example, STI region(s) 55-i or SBregion(s) 57-i, where i=1 and/or 2 and/or 3. For future reference, LDregion 67-2 has lateral width 67-21.

FIGS. 3-9 show simplified cross-sectional views of bipolar transistors20, 20′ of FIGS. 1-2 during various stages of manufacture 803-809yielding structures 903-909, according to further embodiments of theinvention. Referring now to FIGS. 3-4, in manufacturing stages 803, 804substrate 27 is provided comprising (e.g. N type) substrate layer 21with lower surface 22 and upper surface 23 and, in a preferredembodiment, with BOX layer or region 24 (e.g., of silicon oxide)overlying upper surface 23. BOX layer 24 may be omitted in yet otherembodiments. Overlying the combination of substrate layer 21, and BOXlayer 24 when present, is (e.g., P-EPI) SC base layer or region 25 ofvertical thickness 250 and having upper surface 26. Base layer or region25 conveniently has (e.g., P type) doping in the range of about 1E14 to1E16 per cm³, but higher or lower doping can also be used. Thickness 250is usefully in the range of about 0.5 to 15 micrometers, but larger orsmaller thicknesses may also be used. Conventional DTI region 60 having,for example, poly SC core 61 and surrounding dielectric (e.g., siliconoxide) layer 62, is provided extending, for example, from BOX layer 24to upper surface 26, desirably intersecting LD region 67-1. Any form ofDTI region 60 may be used. DTI region 60 is desirable to provide lateralisolation of transistor 20, 20′ but may be omitted in other embodimentswhere such isolation is not needed.

In manufacturing stages 803 and 804, shallow trench isolation (STI)regions 55, 55′ of thickness 56 are provided. STI regions 55, 55′ areconveniently formed of silicon oxide, but other dielectric materials mayalso be used. Thickness 56 is usefully in the range of about 0.1 to 0.8micrometers, but thicker and thinner STI regions may also be used, andSTI regions 55-1, 55-2, 55-3 may have the same or different thicknesses.In manufacturing stage 803 of FIG. 3 for transistor 20, STI regions 55comprise three STI regions 55-1, 55-2, 55-3, where: (a) the lateralseparation between STI regions 55-1 and 55-2 defines collector contactlocation 261, (b) the lateral separation between STI regions 55-2 and55-3 defines base contact location 262, and (c) and the leftward extentof STI region 55-3 defines emitter region location 263. Structure 903results. In manufacturing stage 804 of FIG. 4 for transistor 20′, STIregions 55′ comprise STI regions 55-1 and 55-2. STI region 55-3 isomitted in manufacturing stage 804 of FIG. 4. Structure 904 results frommanufacturing stage 804. Other than the absence of STI region 55-3,structure 904 of FIG. 4 is substantially similar to structure 903 ofFIG. 3. Silicide blocking (SB) region 57-3 (to be applied later) whichtakes the place of STI region 55-3, is shown in dashed outline in FIG.4.

FIGS. 5-9 show an illustrative sequence of doping steps, i.e., ImplantsA-E, but this sequence, while preferred, is not intended to be limiting,and such doping steps may be carried out in other sequences in otherembodiments. For example, Implants A-E may be made in other orders inother embodiments, and such other sequences or orders are intended to beincluded in the claims that follow. Substantially the same manufacturingstages 805-809 of FIGS. 5-9 are used whether structure 903 or 904 is thestarting point. In manufacturing stages 805-809 of FIGS. 5-9 it isassumed, except where specifically noted, that structure 903 is beingused, resulting in device 20 of FIG. 1. Where a particular manufacturingstage would result in slightly different doped regions using structure904, this is noted. But, in general, as far as the formation ofmulti-level collector structure 28 of transistors 20, 20′ is concerned;structures 903 or 904 pass through substantially similar manufacturingstages 805-809 and result in transistors 20, 20′ respectively.

Referring now to manufacturing stage 805 of FIG. 5, structure 903 (or904) has mask 70 applied to upper surface 26, where mask 70 has closedportions 701, 702 and open portion 703. Photo-resist is a non-limitingexample of a suitable material for mask 70 and the further maskssubsequently described. Open portion 703 conveniently encompasses basecontact location 262. Implant A of, for example, a P type impurity, isprovided through opening 703 to form (e.g., P type) doped region 80.Doped region 80 conveniently has a peak doping concentration in therange of about 1E17 to 5E18 per cm³ and depth 801 in the range of about1.5 to 2.5 micrometers from upper surface 26. Depth 801 is somewhatlarger in base contact location 262 and somewhat shallower where ImplantA passes through a portion of STI region 55-2. Structure 905 results,whether starting from structure 903 or 904.

Referring now to manufacturing stage 806 of FIG. 6, mask 70 is removedand replaced with mask 71 having closed portions 711, 712 and openportions 713, 714. Closed portion 711 encompasses collector contactlocation 261 and closed portion 712 encompasses emitter region location263. Open portion 713 extends over parts of LD regions 67-2 (e.g., STIregion 55-2) and, in the case of structure 903, also over part of LDregion 67-3 (e.g., STI region 55-3). In the case of structure 904, theleft edge of mask opening region 713 can be approximately in the samelateral location with respect to base contact location 262 as forstructure 903, but other locations may be used in other embodiments.

Implant B of, for example, a P type impurity, is provided throughopening 713 to form (e.g., P type) doped region 82. Doped region 82conveniently has a peak doping concentration in the range of about 1E16to 5E17 per cm³, preferably about an order of magnitude less than thepeak doping concentration of Implant A of doped region 80. Doped region82 has depth 821 in the range of about 1.0 to 2.0 micrometers from uppersurface 26, being somewhat larger in base contact location 262 (e.g., ofdepth 821) and somewhat shallower in rightward portion 824 (e.g., ofdepth 826) where Implant B passes through a portion of LD region 67-2(e.g., STI region 55-2), and similarly in leftward portion 823 where itpasses through LD region 67-3 (e.g., STI region 55-3) of structure 903.Structure 906 results from manufacturing stage 806, whether startingfrom structure 903 or 904, but with some difference in the shape ofdoped region 82 on the left side of base contact location 262 because ofthe absence of STI region 55-3 in structure 904. For example, there maybe slightly deeper dopant penetration in portion 823 for structure 904.Rightward portion 824 of depth 826 of doped region 82 resulting fromImplant B extends laterally by distance 67-22 toward collector contactlocation 261 to boundary 829. Distance 67-22 is desirably less thanlateral width 67-21 of LD region 67-2 but other distances may be used inother embodiments.

Referring now to manufacturing stage 807 of FIG. 7, mask 71 is removedand replaced with mask 72 having closed portions 721, 722 and openportion 723. Open portion 723 substantially determines the location andlateral extent of multi-layer collector structure 28. Rightward edge 725of closed mask portion 722 determines leftward extent 287 of collectortip or third portion 285. Leftward edge 726 of closed mask portion 721determines the rightward extent of main or first collector portion 281.Rightward edge 829 of doped region 824 substantially determines leftwardextent 289 of main or first collector portion 281 proximate uppersurface 26 and the rightward extent 67-22 of base region portion 251 ofFIGS. 1-2. It will be apparent to those of skill in the art, thatvarious base region portions 251, 252, etc., of FIGS. 1-2 are formed byvarious combinations of Implants A, B and C. For example, base regionportion 824 of FIG. 6 underlying STI region 55-2 is formed by Implant B,while base region portion 251 of FIGS. 1-2 and 7-9 which occupies asubstantially similar space underlying STI region 55-2 is formed by thecombination of Implants B and C. Analogously, base region portions 80,82 of FIG. 6 underlying base contact region location 262 are formed bythe combination of Implants A and B, while base region portion 252 ofFIGS. 1-2 and 7-9 occupying a substantially similar space underlyingbase contact location 262, is formed by the combination of Implants A, B(and C).

Implant C (e.g., N type) is desirably provided into SC base layer orregion 25 through opening 723 of mask 72. In a preferred embodiment,(e.g., N type) multi-level collector structure 28 is substantiallyprovided in a single (e.g., N type) doping operation, albeit taking intoaccount the prior (e.g., P type) doping operations used to form dopedregions 82, 80, 824, etc. However, in other embodiments, multiple (e.g.,N type) doping steps may be used in forming multi-level collector region28. For convenience of description and relating to other figures, afterImplant C, what was referred to in FIG. 6 as portion 824 of doped region82 formed by Implant B underlying STI region 55-2 is referred tohereafter and in FIGS. 1-2 as base region portion 251. Similarly, afterImplant C, the combination of doped regions 80 and 82 of FIG. 6underlying base contact location 262 is referred to hereafter and inFIGS. 1-2 as base region portion 252. It is desirable to use multipledoping steps to form base region portions 251 and 252 so that they canhave somewhat different doping, but other arrangements may also be used.This facilitates providing transistors 20, 20′ having high breakdownvoltages. Stated another way, it is desirable that base region portion252 has a higher doping concentration than base region portion 251,preferably by at least a factor of about 5 higher, but other dopantratios may also be used.

Because of the different (e.g., P type) background doping densities inthe different regions and the channeling effects or lack thereof due tothe presence or absence of STI regions 55-1, 55-2, different collectordepth profiles are obtained in the different portions of collectorstructure 28 even though provided using a single (e.g., N type)collector doping step. For example, in first or main collector portion281, which is substantially unaffected by manufacturing stages 805, 806,the background doping is that provided by (e.g., P-EPI) base region 25.Accordingly, first or main collector portion 281, where it underlies STIregions 55-1, 55-2, has peak dopant concentration usefully in the rangeof about 1E16 to 1E17 per cm³ and extends substantially to depth 291from surface 26 of about 1.5 to 3.5 micrometers. Deeper part 282 offirst or main collector portion 281 substantially underlies collectorcontact location 261 where there is no STI region. Hence, part 282extends further distance 292 of about 0.5 to 2.0 micrometers into (e.g.,P-EPI) base region 25.

Different channeling effects through doped regions 251, 252 and throughpartially overlying LD region 67-2 (e.g., STI region 55-2) lead todifferent depths and different peak dopant concentrations for differentparts of multilevel collector region 28 being formed by Implant C. Forexample, second or central collector portion 283 forms underlying LDregion 67-2 (e.g., STI region 55-2). Second or central collector portion283 has vertical thickness 293 of about 0.5 to 3.5micrometers, depth 294below upper surface 26 of about 0.5 to 2.5 micrometers and peak dopantconcentration usefully in the range of about 1E16 to 1E17 per cm³. Thelower extent of second or central portion 283 is at depth 300 belowupper surface 26. Third or tip collector portion 285 has verticalthickness 295 of about 0.25 to 2.5 micrometers, and is formed underneathcontact region 262 where no LD region is present. Its upper boundary isabout at depth 296 below upper surface 26 of about 1.0 to 3.0micrometers and it has a peak dopant concentration usefully in the rangeof about 5E15 to 1E17 per cm³. Stated another way, implanting third ortip collector portion 285 beneath base contact location 262 throughdoped region 252 and not through overlying LD region 67-2 (e.g., STIregion 55-2) insures that third or tip collector portion 285 will bedeeper than second or central collector portion 283.

Fourth or intermediate collector portion 288, of lateral width 298 andsubstantially vertical extent 299, is formed automatically at thetransition between second or central collector portion 283 and third ortip collector portion 285, where the (e.g., P type) background doping istransitioning between that provided in region or portion 824 by ImplantB to that provided in region or portion 82, 80 by the combination ofImplants A and B. This provides a peak dopant concentration in fourth orintermediate collector region 288 usefully in the range of about 5E15 to1E17 per cm³, width 298 usefully in the range of about 0.01 to 1.0micrometers and vertical extent 299 usefully in the range of about 0.1to 3.0 micrometers, but higher and lower dopant concentrations anddifferent depths and widths may also be used. Fourth or intermediatecollector portion 288 is automatically self-aligned with the leftwardedge of LD region 67-2 (e.g., with STI region 55-2) and with adjoiningcollector portions 283 and 285. Further, as already noted, verticalthickness 299 of fourth or intermediate collector portion 288 will beless than vertical thickness 295 of third or tip collector portion 285,so that fourth or intermediate collector portion 288 is more easilydepleted than adjacent collector portions 285, 283 as the collectorvoltage rises. Manufacturing stage 807 is not affected by the presenceor absence of LD region 67-3 (e.g., STI region 55-3) since that locationis covered and protected by closed portion 722 of mask 72. Structure 907substantially results using either of structures 903 (STI region 55-3 ispresent) or 904 (STI region 55-3 is absent).

Referring now to manufacturing stage 808 of FIG. 8, mask 72 is removedand replaced with mask 73 having closed portions 731, 732 and openportions 733, 734. Open portions 733, 734 correspond to location 261 ofcollector contact region 30 and location 263 of emitter region 34.Implant D (e.g., N+) is provided into SC base region 25 through openings733, 734 of mask 73 to form (e.g., N+) collector contact region 30 ofdepth 31 and (e.g., N+) emitter region 34 of depth 35. Depths 31, 35 maybe the same or different. FIG. 8 shows manufacturing stage 808 andstructure 908 corresponding to structure 903 of device 20 including STIregion 55-3. Persons of skill in the art will understand that forstructure 904 (no STI region 55-3), silicide blocking region 57-3 (seeFIGS. 2 and 4) is applied any time prior to manufacturing stage 808 andserves in place of STI region 55-3 of structure 903 to providesubstantially the same result with respect to emitter region 34 forstructure 904. An alternative process sequence using structure 904 isthat Implant D is provided into SC emitter contact region 34′, whilesilicide block layer 57-3 is formed afterwards within the definedregion. Either method is useful. Structure 908 results, with STI region55-3 present when employing structure 903 and preferably SB region 57-3(e.g., see FIGS. 2 and 4) present when employing structure 904.

Referring now to manufacturing stage 809 of FIG. 9, mask 73 is removedand replaced with mask 74 having closed portions 741, 742 and openportion 743. Open portion 743 corresponds to location 262 of basecontact 32. Implant E (e.g., P+) is provided into SC base layer throughopenings 743 of mask 74 to form (e.g., P+) base contact region 32 ofdepth 33. Structure 909 results. FIG. 9 shows manufacturing stage 809with structure 909 corresponding to structure 903 of device 20 includingSTI region 55-3. Persons of skill in the art will understand that forstructure 904 (no STI region 55-3), silicide blocking region 57-3 (seeFIGS. 2 and 4) serves in place of STI region 55-3 to providesubstantially the same result with respect to base contact region 32.For structure 904, Implant E could be provided into SC base contactregion 32 prior to formation of silicide block layer. Afterwards,silicide block layer 57-3 is formed within the defined region. Eithermethod is useful. Structure 909 results, with those variations discussedabove depending upon whether structure 903 or 904 is used.

As noted earlier, for convenience of explanation, the illustratedsequence of operations has Implants A and B made prior to Implant C, andImplants D and E made after Implant C. However, in other embodiments,Implants A-E may be made in other orders and the method described aboveand the claims that follow are not intended to be limited just to theillustrated sequence.

According to a first embodiment, there is provided a bipolar transistor(20, 20′), comprising, a substrate (27) having a semiconductor baseregion (25) of a first conductivity type at least in part proximate anupper substrate surface (26), and a multi-level collector structure (28)of a second, opposite, conductivity type located in the semiconductorbase region (25), wherein the multi-level collector structure comprisesa central collector portion (283) of a first vertical extent (293)underlying a first part (251) of the base region (25), a collector tipportion (285) of a second vertical extent (295) underlying another part(252) of the base region (25) and separated from the central collectorportion (283) by an intermediate collector portion (288) of a thirdvertical extent (299) different than the second vertical extent (295).According to a further embodiment, the third vertical extent (299) is ina range of about 1% to 90% of the second vertical extent (295).According to a still further embodiment, the third vertical extent (299)is in a range of about 15% to 80% of the second vertical extent (295).According to a yet further embodiment, the multilevel collectorstructure (28) is substantially surrounded on all sides by parts (251,252, 254, 255, 256) of the base region (25) except where the collectorstructure (28) extends to a collector contact region (30). According toa still yet further embodiment, the central collector portion (283) liesat a first depth (294) beneath the upper surface (26) and the collectortip portion (285) lies at a second depth (296) beneath the uppersubstrate surface (26) different from the first depth (294). Accordingto a yet still further embodiment, the collector tip portion (285) has afirst lateral width (284) and the intermediate collector portion (288)has a second lateral width (298) different than the first lateral width(284). According to another embodiment, the transistor (20, 20′) furthercomprises a base contact region (32) and wherein the collector tipportion (285) underlies at least a portion of the base contact region(32). According to still another embodiment, the transistor (20, 20′)further comprises a shallow trench isolation region (55-2) proximate theupper surface (26) overlying the first part (251) of the base region(25). According to yet another embodiment, the transistor (20, 20′)further comprises an emitter region (34) of the second conductivity typein the base region (25) laterally spaced apart from the collector tipportion (285), a base contact region (32) of the first conductivity typein the base region (25) at least in part overlying the collector tipportion (285) and a collector contact region (30) of the firstconductivity type laterally spaced apart from the base contact region(32) and Ohmically coupled to the central collector portion (283).According to still yet another embodiment, the first part (251) of thebase region (25) extends laterally from the base contact region (32)toward the collector contact region (30).

According to a second embodiment, there is provided a method for forminga bipolar transistor (20, 20′) comprising, providing a substrate (27)having therein a semiconductor base region (25) of a first conductivitytype and first doping density proximate an upper substrate surface (26),and forming in the base region (25) a multilevel collector structure(28) of a second opposite conductivity type and having a first collectorpart (281) extending to a collector contact (30), a second collectorpart (283) Ohmically coupled to the first collector part (281)underlying the upper substrate surface (26) by a first depth (294), athird collector part (285) laterally spaced apart from the secondcollector part (283) and underlying the upper substrate surface (26) bya second depth (296) and having a first vertical thickness (295), and afourth collector part (288) Ohmically coupling the second (283) andthird (285) collector parts and having a second vertical thickness (299)different than the first vertical thickness (295). According to afurther embodiment, the step of forming in the base region (25) amultilevel collector structure (28) of a second opposite conductivitytype occurs during a common second conductivity type doping procedure.According to a still further embodiment, the method further comprisesprior to the step of forming the multilevel collector structure (28),forming a shallow trench isolation (STI) region (55-2) proximate theupper substrate surface (26) and substantially forming the secondcollector part (283) by implanting a dopant of the second conductivitytype through the STI region (55-2). According to a yet furtherembodiment, the method comprises before or after forming the multilevelcollector structure, adding impurities of the first conductivity type inregions (80, 82, 824) overlying regions occupied or to be subsequentlyoccupied by the second (283), third (285) and fourth (288) collectorparts. According to a still yet further embodiment, the method comprisesforming proximate the upper substrate surface (26) a lateral dielectric(LD) region (67-3) laterally spaced apart from the second collector part(285), the LD region (67-3) substantially determining lateral separationof an emitter region (34) and a base contact region (32). According to ayet still further embodiment, the LD region (67-3) is a shallow trenchisolation (STI) region (55-3). According to another embodiment, the LDregion (67-3) is a metal-semiconductor alloy blocking region (57-3).

According to a third embodiment, there is provided a bipolar transistor(20, 20′) having an upper surface (26), comprising, an emitter region(34), a base contact region (32) and a collector contact region (30)proximate the upper surface (26), a multilevel collector structure (28)comprising, a first part (281) of a first vertical extent (291) coupledto the collector contact region (30), an adjacent second part (283)having a second vertical extent (293), a third part (285) coupled to thesecond part (283) and of a depth (296), and a fourth part (288) having afourth vertical extent (299) coupling the second part (283) and thethird part (285), and a first base region portion (251) overlying thesecond part (283), a second base region portion (252) separating thethird part (285) from the base contact region (32), and other baseregion portions (254, 256, 255) laterally surrounding and underlying themultilevel collector structure (28). According to a further embodiment,the bipolar transistor (20, 20′) further comprises a first lateraldielectric (LD) region (67-2) laterally separating the collector contactregion (30) and the base contact region (32) and a second LD region(67-3) laterally separating the base contact region (32) and the emitterregion (34). According to a still further embodiment, the first LDregion (67-2) is a shallow trench isolation (STI) region (55-2) and thesecond LD region (67-3) is a further STI region (55-3) or a silicideblocking (SB) region (57-3).

While at least one exemplary embodiment and method of fabrication hasbeen presented in the foregoing detailed description of the invention,it should be appreciated that a vast number of variations exist. Itshould also be appreciated that the exemplary embodiment or exemplaryembodiments are only examples, and are not intended to limit the scope,applicability, or configuration of the invention in any way. Rather, theforegoing detailed description will provide those skilled in the artwith a convenient road map for implementing an exemplary embodiment ofthe invention, it being understood that various changes may be made inthe function and arrangement of elements described in an exemplaryembodiment without departing from the scope of the invention as setforth in the appended claims and their legal equivalents.

What is claimed is:
 1. A bipolar transistor (20, 20′), comprising: asubstrate (27) having a semiconductor base region (25) of a firstconductivity type at least in part proximate an upper substrate surface(26); and a multi-level collector structure (28) of a second, opposite,conductivity type located in the semiconductor base region (25), whereinthe multi-level collector structure comprises a central collectorportion (283) of a first vertical extent (293) underlying a first part(251) of the base region (25), a collector tip portion (285) of a secondvertical extent (295) underlying another part (252) of the base region(25) and separated from the central collector portion (283) by anintermediate collector portion (288) of a third vertical extent (299)different than the second vertical extent (295).
 2. The bipolartransistor (20, 20′) of claim 1, wherein the third vertical extent (299)is in a range of about 1% to 90% of the second vertical extent (295). 3.The bipolar transistor (20, 20′) of claim 2, wherein the third verticalextent (299) is in a range of about 15% to 80% of the second verticalextent (295).
 4. The bipolar transistor (20, 20′) of claim 1, whereinthe multilevel collector structure (28) is substantially surrounded onall sides by parts (251, 252, 254, 255, 256) of the base region (25)except where the collector structure (28) extends to a collector contactregion (30).
 5. The bipolar transistor (20, 20′) of claim 1, wherein thecentral collector portion (283) lies at a first depth (294) beneath theupper surface (26) and the collector tip portion (285) lies at a seconddepth (296) beneath the upper substrate surface (26) different from thefirst depth (294).
 6. The bipolar transistor (20, 20′) of claim 1,wherein the collector tip portion (285) has a first lateral width (284)and the intermediate collector portion (288) has a second lateral width(298) different than the first lateral width (284).
 7. The bipolartransistor (20, 20′) of claim 1, further comprising a base contactregion (32) and wherein the collector tip portion (285) underlies atleast a portion of the base contact region (32).
 8. The bipolartransistor (20, 20′) of claim 1, further comprising a shallow trenchisolation region (55-2) proximate the upper surface (26) overlying thefirst part (251) of the base region (25).
 9. The bipolar transistor (20,20′) of claim 1, further comprising an emitter region (34) of the secondconductivity type in the base region (25) laterally spaced apart fromthe collector tip portion (285), a base contact region (32) of the firstconductivity type in the base region (25) at least in part overlying thecollector tip portion (285) and a collector contact region (30) of thefirst conductivity type laterally spaced apart from the base contactregion (32) and Ohmically coupled to the central collector portion(283).
 10. The bipolar transistor (20, 20′) of claim 9, wherein thefirst part (251) of the base region (25) extends laterally from the basecontact region (32) toward the collector contact region (30).
 11. Amethod for forming a bipolar transistor (20, 20′) comprising: providinga substrate (27) having therein a semiconductor base region (25) of afirst conductivity type and first doping density proximate an uppersubstrate surface (26); and forming in the base region (25) a multilevelcollector structure (28) of a second opposite conductivity type andhaving a first collector part (281) extending to a collector contact(30), a second collector part (283) Ohmically coupled to the firstcollector part (281) underlying the upper substrate surface (26) by afirst depth (294), a third collector part (285) laterally spaced apartfrom the second collector part (283) and underlying the upper substratesurface (26) by a second depth (296) and having a first verticalthickness (295), and a fourth collector part (288) Ohmically couplingthe second (283) and third (285) collector parts and having a secondvertical thickness (299) different than the first vertical thickness(295).
 12. The method for forming a bipolar transistor (20, 20′) ofclaim 11, wherein the step of forming in the base region (25) amultilevel collector structure (28) of a second opposite conductivitytype occurs during a common second conductivity type doping procedure.13. The method for forming a bipolar transistor (20, 20′) of claim 11,further comprising, prior to the step of forming the multilevelcollector structure (28), forming a shallow trench isolation (STI)region (55-2) proximate the upper substrate surface (26) andsubstantially forming the second collector part (283) by implanting adopant of the second conductivity type through the STI region (55-2).14. The method for forming a bipolar transistor (20, 20′) of claim 11,further comprising, before or after forming the multilevel collectorstructure, adding impurities of the first conductivity type in regions(80, 82, 824) overlying regions occupied or to be subsequently occupiedby the second (283), third (285) and fourth (288) collector parts. 15.The method for forming a bipolar transistor (20, 20′) of claim 11,further comprising forming proximate the upper substrate surface (26) alateral dielectric (LD) region (67-3) laterally spaced apart from thesecond collector part (285), the LD region (67-3) substantiallydetermining lateral separation of an emitter region (34) and a basecontact region (32).
 16. The method for forming a bipolar transistor(20, 20′) of claim 15, wherein the LD region (67-3) is a shallow trenchisolation (STI) region (55-3).
 17. The method for forming a bipolartransistor (20, 20′) of claim 15, wherein the LD region (67-3) is ametal-semiconductor alloy blocking region (57-3).
 18. A bipolartransistor (20, 20′) having an upper surface (26), comprising: anemitter region (34), a base contact region (32) and a collector contactregion (30) proximate the upper surface (26); a multilevel collectorstructure (28) comprising, a first part (281) of a first vertical extent(291) coupled to the collector contact region (30), an adjacent secondpart (283) having a second vertical extent (293), a third part (285)coupled to the second part (283) and of a depth (296), and a fourth part(288) having a fourth vertical extent (299) coupling the second part(283) and the third part (285); and a first base region portion (251)overlying the second part (283), a second base region portion (252)separating the third part (285) from the base contact region (32), andother base region portions (254, 256, 255) laterally surrounding andunderlying the multilevel collector structure (28).
 19. The bipolartransistor (20, 20′) of claim 18, further comprising a first lateraldielectric (LD) region (67-2) laterally separating the collector contactregion (30) and the base contact region (32) and a second LD region(67-3) laterally separating the base contact region (32) and the emitterregion (34).
 20. The bipolar transistor (20, 20′) of claim 19, whereinthe first LD region (67-2) is a shallow trench isolation (STI) region(55-2) and the second LD region (67-3) is a further STI region (55-3) ora silicide blocking (SB) region (57-3).